1. Field of the Invention
This invention relates to a resin sealing method and device for chip size packages.
2. Description of the Related Art
The chip size packages (hereinafer referred to as "CSP") are formed substantially in the same size as a semiconductor chip, and as one of the CSPs, there is an SON (small outline nonlead) package. FIGS. 1 and 2 are a sectional view and a bottom view of the CSP, particularly SON, respectively. In FIG. 1, reference numeral 10 denotes a semiconductor chip; 112 denotes a die pad; and 114 is leads for electrically connecting the semiconductor chip 10 and a package substrate. Each of the leads 114 is formed as a bonding part 114a joined to the semiconductor chip 10 at a center thereof with the surface of a joint electrically connected to an electrode of the semiconductor chip 10 by wire bonding. An outer portion of each of the bonding parts 114a is formed as a connection part 114b slightly floating up from the chip face and extending in parallel with the chip face for connection to the package substrate.
Each of the connection parts 114b is placed in the chip face of the semiconductor chip 10 and the whole package is formed substantially in a chip size. Reference numeral 116 denotes bonding wires for electrically connecting the electrode of the semiconductor chip 10 and each of the leads 114. Reference numeral 18 denotes a sealing resin for sealing the joint faces to the leads 114 of the semiconductor chip 10. The sealing resin 18 seals the wiring bonding portions of the semiconductor chip 10 and the leads 114 and also supports the connection parts 114b, of the leads 114 at predetermined positions.
The connection part 114b of each the respective lead 114 is exposed to the outer face of the sealing resin 18 for connection to the package substrate by soldering, etc. In the example shown in FIGS. 1 and 2, the connection parts 114b are placed in parallel with a given spacing on two opposed sides on the outer face of the sealing resin 18. They are formed on a flat face so that they can be connected to the connection parts of the package substrate by soldering, etc.
If a normal transfer mold method is used to seal the joint faces of the semiconductor chip 10 and the leads 114 with a resin in a manufacturing process of CSPs as described above, resin fins may occur on the surfaces of the leads 114. Thus, because the normal transfer mold method cannot be used and hitherto, a potting method has been used to seal with a resin. Since the CSP has a large number of leads 114 placed in parallel with the chip face, it is placed in portrait orientation and a potting resin is injected.
However, the potting method involves the following problems: It takes much time until the resin hardens, and mass productivity is poor. Air is easily caught in the resin at the potting time, whereby voids easily occur. Close adherence of the resin to the semiconductor chip 10 is not necessarily sufficient. The potting method is lower in resin molding accuracy than the resin sealing method using a transfer mold. Voids occurring in the package cause cracks to occur due to heat at a curing process. After packaging, temperature rise and drop in the external environment act repeatedly on the package, thereby breaking the package or short-circuiting the wiring pattern.
FIGS. 3A to 3D show other product examples of the CSP. For a product shown in FIG. 3A, a wiring pattern 212 is provided via an electric insulating layer 211 on a face where surface electrodes of a semiconductor chip 10 are placed, and solder balls 214 are joined as external connection pins. The solder balls 214 are connected to one end of the wiring pattern 212 and the other end of the wiring pattern 212 is extended like leads from the periphery of the electric insulating layer 211 to the outside and are bonded to the surface electrodes 216 of the semiconductor chip 10.
A sealing resin 18 of the wiring pattern 212 is bonded to the surface electrodes 216. Hitherto, the wiring pattern 212 of the portion bonded to the surface electrodes 216 has been sealed by potting. The reason why it has been sealed by potting is as follows: Since the wiring pattern 212 in the chip size package is supported via the electric insulating layer 211 on the semiconductor chip 10, if the wiring pattern 212 is sealed with a resin by a normal transfer mold method, a molded article (an object to be molded) cannot reliably be pressed and a resin fin occurs in an unnecessary part and when a runner is peeled off or a gate is broken after the wiring pattern 212 is sealed with the resin, the wiring pattern may be damaged.
FIG. 3B shows a structure in which a semiconductor chip 10 is housed in a ring 120 shaped like a rectangular frame and FIG. 3C shows a structure in which a semiconductor chip 1(is housed in a can 222 as other product examples of CSPs. FIG. 3D shows a fan-in/fan-out type product wherein the semiconductor chip 10 is supported on a package substrate 224 formed with a recess for housing the semiconductor chip 10 and a wiring pattern 212 is provided in each of an inner area and an outer area of the semiconductor chip 10 and external connection pins are bonded. For every example shown in FIGS. 3B, 3C and 3D, the wiring pattern 212 of the portion bonded to the surface electrodes 216 of the semiconductor chip 10 is sealed by potting.